This application claims the priority of Korean Patent Application No. 2003-42766, filed on Jun. 27, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and a method of fabricating the same, and more particularly to an ultra short channel MOSFET having a channel of nm dimension and a method of fabricating the same.
2. Description of the Related Art
As the dimensions of silicon semiconductor devices decrease in order to attain low power dissipation, high packing density and high-speed operation, it is especially necessary in a MOSFET to secure a shrunken channel length, shallower junction depth of source and drain regions and a thinner gate oxide layer. Also, even in devices with equal dimensions, performance can be improved by increasing driving current and decreasing leakage current. However, a transistor of microscopic dimensions fabricated using a typical process requires highly strict processing conditions and very expensive processing equipment to reduce the channel length.
For example, a micro-device having a channel of nm dimension cannot be fabricated by a conventional photolithography process but must be fabricated using a pattern formation technique that uses e-beam direct writing, Extreme Ultra Violet (EUV) exposure or X-ray exposure. Thus, fabricating costs of the silicon device are large and mass production is very difficult. Furthermore, conventional source and drain formation techniques such as ion implantation or plasma doping not only involve a difficulty in forming a shallow junction, but also produce a defect in a substrate resulting from implantation, thereby degrading device characteristics and requiring demanding highly expensive junction forming equipment.
Moreover, as device dimensions are decreased, the gate oxide layer becomes thinner, resulting in a possible gate leakage current. Research has done into finding a material with a higher dielectric constant as a gate oxide layer so as to decrease the gate leakage current. However, in a conventional device, since the gate oxide layer is formed prior to forming a source and a drain formed by ion implantation, a processing temperature of a subsequent activating thermal treatment is restricted.
A replacement gate structure has been suggested as an alternative but requires a fabrication process in which a self-aligning process of the gate and source/drain is highly complicated. Accordingly, a process of fabricating a microscopic device is required for solving the above-enumerated problems and embodying an integrated circuit with high packing density and high performance.